The tree-structured distributed network front-end processor architecture

Contemporary front-end processors, such as the IBM 3705,1 Memorex 1380, Burroughs Data Communications Processor3 and the MERIT Communications Controller, 4 share the same general architecture depicted in Figure 1. Communication !ines are associated on a one-on-one basis with line adapters. These are connected in small groups (clusters) to the local processor, and perhaps to the local memory, through line interface bases. In a similar manner, the host system input/output channels are associated on a one-onone basis with channel adapters which are connected to the local processor and memory. The architecture can be thought of as a minicomputer system in which the channel adapters and line interface base/line adapter subsystems are input/output devices. In fact, many front-end processors are configured in precisely this fashion. There are many design parameters which can be varied to affect the maximum aggregate data rate, cost, and servicesrendered characteristics of front-end processors. The number of line adapters per line interface base and their relative complexities are an example. The line interface bases might interrupt the processor for every character or transfer entire records by means of direct memory accesses. The channel adapters might connect directly to the host system channels or through some other standard interface such as a channelto-channel adapter or high-speed communication line. Generally channel adapters utilize direct memory access features because of the high aggregate data rates they sustain. All of the intelligence of a typical front-end processor is iocated in the single local uni-processor. This uni-processor must handle all the interrupts from the line and channel adapters. In effect it is multiprogrammed across all of the data streams to provide front-end services such as line editing, character code translation, and message formatting. Saturation of the local processor limits the kinds of services that can be provided and the aggregate data rate that can be sustained. We describe here a front-end processor architecture in which the single local uni-processor, memory, line interface bases and line adapters are replaced with a network of microprocessor systems as depicted in Figure 2. The network